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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
    • Topologies and Bridges
    • AXI Integration Details
    • Ordering and Deadlock at the Top
    • QoS and Arbitration
    • NoC Basics
    • Coherent Interconnect View
    • Firewalls and Protection
      • Secure-Access Filters
      • Address-Range Firewalls and Master IDs
      • Failure Modes and Debug
    • Bandwidth and Latency Verification
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Firewalls and Protection
  1. Topics
  2. SoC Design
  3. Interconnect and Bus Fabrics
  4. Firewalls and Protection
  5. Failure Modes and Debug
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    Part 4 of 14, lesson 23 of 26Part 4 of 14/Interconnect and Bus Fabrics/Lesson 23 of 26All levels

    Failure Modes and Debug

    Telling secure faults from decode errors: the response table as a diagnostic, and the debug order that finds the filter.

    Why it matters

    A driver reports an access that traps, and several different faults look identical from the core: an unmapped address, a secure denial, a reserved slot and an unmapped register offset all arrive as a bus error. Guessing wastes the afternoon; reading the response code against the map takes a minute. This lesson turns the error table into a diagnostic drill.

    The core idea

    The drill has three steps. First, classify by response: DECERR means no slave claimed the address, so look for the map holes H1, H2 and H4. SLVERR means something below the interconnect answered no: a security refusal, a reserved APB slot (H3), or an unmapped register offset inside a slave. SLVERR is therefore not proof that the address is a real register. Second, localise by level: a refusal from inside the APB window points at the slot check or the APB default slave, a refusal on SRAM1 points at the interconnect filter. Third, reproduce from both states: the same access from secure and non-secure, and from CPU and SBR where both can reach, splits attribute bugs from wiring bugs. The table below is the whole drill on NanoSoC addresses.

    Diagram
    # not-run: NanoSoC denial diagnosis table, NanoSoC teaching values
    0x2001_0000 non-secure .... SLVERR from interconnect filter: secure-only region.
    0x4000_6000 non-secure .... SLVERR via PSLVERR: secure-only RSTPWR slot.
    0x4000_7000 either state ... SLVERR via PSLVERR: H3 reserved, APB default slave.
    0x4000_0014 either state ... SLVERR via PSLVERR: DMA offset 0x14 is unmapped (0x14 to 0xFF).
    0x4000_0100 either state ... completes, no error: alias of the DMA at 0x4000_0000.
    0x5000_0000 either state ... DECERR: hole H4, no select, interconnect default.
    SBR job from SRAM1, NS set . SBR STATUS.ERR on beat zero: master attribute.
    Same job, NS cleared ..... completes: attribute fixed, wiring proved good.

    What the review looks for

    • The fault handler logs address, response code and security state, so field returns carry the diagnosis.

    • The diagnosis table above, or its equivalent, is in the integration specification with the responder named per row.

    • No production software treats a denial as a retryable error: denials are deterministic and retrying hides attacks.

    Verify and debug

    Sweep the denial table from software during bring-up: one access per row, confirming each code from each state. If a row that should deny instead hangs, the error path is broken, not the policy: check the default slave, the denied-burst responder and the bridge error propagation before touching any filter. If a row that should allow denies, read the filter attribute and the master sideband at the filter inputs; the mismatch is visible there. Do not read SLVERR as mapped: confirm the offset against the register map, because three different causes share the code.

    Retrying a deterministic denial: driver code treats SLVERR like a transient bus error and retries, turning a one-cycle refusal into a loop that looks like a hang. Denials are policy, so the handler must log and trap, and the retry budget belongs only to genuinely transient errors.

    If asked to debug an access fault, narrate the three steps before touching the design: classify by code, localise by level, reproduce across states. Then give one NanoSoC row per outcome to show the table is memorised, not the method.

    Check yourself Non-secure access to 0x4000_7000 returns SLVERR. Policy bug or correct behaviour?

    Correct behaviour: H3 is reserved and the APB default slave answers PSLVERR, which the bridge turns into SLVERR. The fix for the driver is to stop going there, not to relax any filter.

    Related topics

    • Address-Range Firewalls and Master IDs

    • Next: Bandwidth and Latency Verification

    • Hardware Debug: Hangs and Deadlocks

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    See also

    • Secure-Access Filters