What is a package for, which families exist, and why does NanoSoC use the one it does? Ball rules are the next lesson; supply paths through the package are the next topic. The package matters first because it fixes two budgets at once: the number of balls available for the 31 pads, and the inductance of every supply path the noise and power lessons compute with.
Packages divide along two axes. The die connection is either wire-bond, with thin wires from a ring of pads at the die edge to the package, or flip-chip, with bumps across the die face mated straight to the package. Wire-bond suits low pin counts and low cost and matches a perimeter pad ring; every supply goes through a wire with real inductance. Flip-chip suits higher counts and better power delivery, because bumps are short and supplies can sit beside their consumers, at the cost of bump planning across the die and a redistribution layer if the I/O cells stay in a ring. The board connection is either leaded at the perimeter or an array of balls underneath: perimeters are cheap and inspectable, arrays carry more balls in less area and escape through via channels the third lesson prices.
NanoSoC's teaching choice is a small leadless ball-array package with the die wire-bonded from a perimeter pad ring. It matches the ring the first topic drew and the perimeter arithmetic of the pad-count topic, and with only 31 pads and a core-limited die there is no pressure that would justify flip-chip. Flip-chip stays in the table as the rejected option, and the lessons on power delivery show what the choice costs in supply inductance. The table compares the families at the concept level; no number in it describes any vendor's product.
Family | Die connection | Board connection | When it fits | What it costs |
|---|---|---|---|---|
Wire-bond, leaded perimeter | Edge wires | Leads | Few pins, cost-driven chips | High supply inductance; no array density. |
Wire-bond, ball array (NanoSoC teaching choice) | Edge wires from a perimeter ring | Full ball array | Modest pin count, board density wanted, die set by the core | Wire inductance on every supply; pads limited to the perimeter. |
Flip-chip, ball array (rejected) | Face bumps | Full ball array | Power integrity or pin count dominates | Bump map planning; package cost above wire-bond; pays off only when the perimeter limits the die. |
A note on inductance: from die to package the connection is a bond wire (about a nanohenry, the larger) or a flip-chip bump (tens of picohenries). The package traces and the ball add to either, and the next topic prices them. NanoSoC's supply pairs therefore sit as close to the die as the ring allows, and the decoupling lesson puts capacitors beside them.
import math
PADS, EXTENSION = 31, 7 # NanoSoC v1 pads; optional test and boot pins
def smallest_array(pads):
n = math.ceil(math.sqrt(pads))
return n, n * n
n, balls = smallest_array(PADS)
assert (n, balls) == (6, 36), (n, balls)
spare = balls - PADS
assert spare == 5 and round(100 * spare / balls, 1) == 13.9
assert not PADS <= 5 * 5 # a 5 x 5 = 25 ball array cannot hold 31 pads
n2, balls2 = smallest_array(PADS + EXTENSION)
assert (n2, balls2) == (7, 49), (n2, balls2) # the extension forces a bigger array
print("PASS: 31 pads fit a 6 x 6 = 36 ball array with 5 spare (13.9%); 5 x 5 fails; with 7 extension pads 7 x 7 = 49")The package family named with the reason: which budget (pins, power integrity or cost) decided it.
Ball count covering all pads plus spares, with the spare balls listed.
The inductance of the die connection acknowledged wherever a lesson assumes a short supply path.
Verify the fit on paper: pads plus no-connect balls must fit the array, with a few spare sites left for a later respin. If the array overflows, the choice is a bigger array or fewer pins, never tighter escape channels, which belong to the board team to approve, not the chip team to assume.
Because the die is core-limited with a perimeter that holds the 31 pads with room to spare, so nothing forces area-array bumps, and a wire-bonded ring is cheaper and matches the ring drawn in the first topic. A chip whose perimeter limited its die, or whose supply noise could not be met with wires, would choose flip-chip.