RTL simulation proves the design as written; the chip is built from the netlist as synthesised, placed and powered. Gate-level simulation closes the first gap — what the tools changed — and power-aware simulation closes the second — what the power intent adds. On NanoSoC these two runs find the failure classes RTL cannot show: an ECO the equivalence check missed, an X the RTL optimised away, two missing isolation clamps, a restore that runs before power is stable. This topic teaches both lenses, what each costs, and when each runs.
Lesson | After it you can... |
|---|---|
Say what GLS adds over RTL and run it after every netlist change. | |
Read an X to its source and prove the reset order in the netlist. | |
Check isolation, retention and sequencing with the power intent active. |
Suggested order: top to bottom. Gate-level first, because it replays the known-good RTL tests on the netlist; then the X and reset analysis, which is where most GLS debug time goes; then power-aware, which adds the intent dimension. For the debug-side view see the gate-level lesson linked below; this topic is the integrator's when-and-what. The ten planted bugs it refers to are listed in the NanoSoC tour.
Its job is fidelity, not function: same stimulus on both models, and any divergence is a netlist or timing fact. New tests would confound function bugs with fidelity bugs.