The sweeps prove the wires; only software proves the chip does its job. Firmware co-simulation runs the actual boot ROM against the RTL — the same reset vector, the same stack setup, the same SPI load — and watches it reach the prompt. On NanoSoC that run is 12.581 ms of simulated time and exercises every block in its real sequence for the first time. This topic teaches that run: how the code meets the RTL, where the checkpoints go (on the bench, not in the ROM), what the self-test proves, and what the run costs. For the general method see the co-verification lesson linked below; this topic is the NanoSoC boot, staged and priced. The ROM, its wake path and its checksum are designed in Boot ROM and Boot Modes; this topic runs that code.
Lesson | After it you can... |
|---|---|
Set up the ROM-in-simulation run and say what it proves that sweeps cannot. | |
Place bench-side checkpoints through the boot and read a failure to its stage. | |
Price a firmware run and choose logging that debugs without drowning. |
Suggested order: top to bottom. The run first, because setup decisions constrain everything; then the bench checkpoints around it, which turn a hang into a stage number; then the cost and logging, which decide how often the run executes. The performance topic next door assumes this run passes and measures on top of it.
A wiring bug found by boot costs the whole 12.581 ms run per iteration plus firmware debug; found by sweep it costs one 125 ns access. Order is by failure cost, not by importance.