Functional tests prove the chip works; performance verification proves it works fast enough. NanoSoC publishes a full budget table — per-link peak and sustained bandwidth, per-access latency, the interrupt path — and this topic is the method that checks it: what traffic to drive, where the counters sit, and how to read a miss back to arbitration, banking or burst efficiency. The budget tables and the same-bank trap are derived link by link in Bandwidth and Latency Verification; what is new here is the chip-level work: traffic generators and counters on the integrated chip, a measurement that can fail, and reading a miss back to its cause. The method is taught in full on NanoSoC numbers.

Suggested order: top to bottom. Bandwidth first, because throughput failures are the commonest and the traffic is the simplest; then latency, which needs the blocking discipline; then the monitors and the miss analysis, which consume both. For the general theory see the performance-and-power verification lesson linked from each page; the budgets themselves belong to this section.

Related topics

• NanoSoC Tour

• Bus Fabrics: Bandwidth and Latency Verification

• Bus Fabrics: QoS and Arbitration

• Interrupts and DMA: Interrupt Routing and Latency