Connectivity tests are the cheapest tests on the plan and the ones with the best record: one forced toggle per wire, one read per reset value, one access per hole. On NanoSoC they catch the wiring, map, reset and power-intent bugs (1, 2, 3, 4 and 6) and expose the two contract bugs (9 and 10) to a directed register access, all before the boot test ever runs. The ten planted bugs are listed in the NanoSoC tour; the whole-chip alias and hole checks are taught from the map side in Memory-Map Verification, and this topic does not repeat them. This topic implements the three sweep families — registers, map and wiring, reset and clocks — and maps each check to the bug it catches, so a failure points at wiring instead of starting a debug expedition. Its companions are the formal connectivity and bind-checker lessons elsewhere; this topic is the simulated sweep that runs on every change.
Lesson | After it you can... |
|---|---|
Sweep every register for reset values, access types and the DMA traps. | |
Prove the map answers, the holes error, the alias repeats and each interrupt reaches its input. | |
Prove release order, clock delivery and isolation presence in one short test. |
Suggested order: top to bottom. Registers first, because every later test programs registers to do its job; then the map and wiring, which prove the addresses those programs touch; then reset, clock and power sanity, which prove the chip is alive enough for either. The firmware topic next door consumes all three: it assumes the sweeps pass.
A sweep costs one access per check — a CPU read of a DMA or SBR register takes 125 ns and a clk_per register 281.25 ns — and catches wiring bugs at the price of a single transaction; a boot costs 12.581 ms of slow firmware simulation per iteration.