The DMA arrives with a passing bench, the interconnect with a clean lint report, and the chip still hangs on its first DMA job. Each piece was verified where its bugs are cheapest, but the wiring between them was verified nowhere. This topic draws the boundary lines (the ten planted bugs it uses are listed in the NanoSoC tour): which tests belong at block, subsystem and chip level, the concrete top-level test list for NanoSoC, and how reuse and regression turn that list into signoff evidence. For the general theory of levels, reuse and co-verification see the verification-first-principles course; this topic is the NanoSoC instance, with names, addresses and numbers.
Lesson | After it you can... |
|---|---|
Assign any test to its cheapest level and name the failures only the top can catch. | |
Enumerate the top-level tests and say which planted bug each one catches. | |
Reuse block collateral at the top and size a regression that fits the schedule. |
Suggested order: top to bottom. Levels first, because the level rule judges every later test; then the concrete list, which is the levels applied to NanoSoC; then reuse and regression, which execute the list. The next topic takes the cheapest entries on that list — the connectivity tests — and implements them.
The bench replaces the chip around the block: its neighbours are models, so wiring, addresses, clocks, resets and power across the boundary were never exercised.