Why it matters

Strategy without a list is a wish. The integrator's test list is short enough to memorise and complete enough that every planted bug trips at least one entry. Its one job is that list: ten groups, each with a stated target and a named bug it catches, ordered so the cheapest tests run first and the expensive ones earn their keep.

The core idea

The list runs in risk order, cheapest first. Connectivity proves the wires: one forced toggle per interrupt into the RAW register, one read per reset value, one write per clock enable. The memory-map sweep proves the decoders: one access per region, one per hole with the expected DECERR or SLVERR, one alias pair proving the DMA repeats sixteen times. Register sweeps prove reset values and access types against the register tables, including the DMA traps: LEN and KEY silently ignored while BUSY, ERR sticky across GO, CTRL bit 1 rewriting IRQ_EN on every write. Boot to banner proves the ROM flow end to end, with a bench monitor timestamping each stage (the ROM itself prints only the banner). Interrupt end to end proves each source raises irq_cpu and the handler clears it, with the DMA job as the flagship. The DMA stream proves a 64-word job in 72 system clocks with the checksum compared. Power-state walk proves SLEEP entry and wake with retention. Reset-order proves the staged release and the software-reset scope. Security proves secure-only regions reject non-secure access, and that non-secure software cannot make the SBR issue secure accesses. The second check fails on NanoSoC v1: the SBR slot is non-secure and its NS bit is writable, so the partition is not closed until the bit is made secure-writable. Performance proves the bandwidth and latency table, which has its own topic.

# not-run: ordering arithmetic, NanoSoC teaching values
# Cheapest-first order keeps debug cheap: connectivity and map sweeps run in
# milliseconds of simulated time and catch wiring bugs before the 12.581 ms
# boot test ever runs. A wiring bug found by boot costs the whole boot per
# iteration; found by sweep it costs one register access (a CPU read of a DMA or SBR register takes 125 ns; a clk_per register such as INTC RAW takes 281.25 ns).

What the review looks for

• Every planted bug names at least one group above; every group names at least one bug or budget it guards.

• The boot test asserts the 12.581 ms total and the 86.9 percent SPI share, so a slowdown points at its stage.

• Security tests touch both directions: secure may enter SRAM1 and RSTPWR, non-secure must be refused with an error response (SLVERR for SRAM1). One test is expected to fail until the SBR weakness is fixed, and it stays in the list as a named open item.

Verify and debug

Run the list top to bottom on every integration change: stop at the first red group, because a connectivity failure explains most boot failures and a map failure explains most driver failures. Keep each group independent so a power-walk failure never blocks the register sweep; independence is what makes the list bisectable. For the method behind software-driven chip tests see the co-verification lesson linked below.

Related topics

• Levels and What Only the Chip Can Show

• Next: Reuse, Regression and Signoff Evidence

• Chip Signoff: Tapeout Readiness Review

• Verification First Principles: Hardware-Software Co-Verification