Accelerator Design Patterns — Step-by-Step Walkthrough

Step-by-step analysis walkthrough

Follow this walkthrough when you own Accelerator Design Patterns in a performance review or architecture signoff meeting.

1. Confirm workload and analysis tag.

2. Open Accelerator pattern decision matrix and capture worst cluster.

3. Classify bottleneck type.

4. Map cluster to structure.

5. List competing hypotheses.

6. Run cheapest falsifying experiment.

7. Estimate metric delta.

8. Choose bounded change.

9. List regression surfaces.

10. Replay workloads.

11. Write decision memo.

12. Capture methodology guardrail.

Artifacts to collect

• Workload list

• PMU/trace config

• Metric dashboard

• Decision memo

Decision memo template

DECISION MEMO — Accelerator Design Patterns
metric:
hypothesis:
experiment:
decision:
validation:

Architecture deep dive

Accelerators win on locality and bandwidth contracts, not peak OPS alone.

Concept diagram

ACCELERATOR DATAFLOW

Host CPU ── commands ──► Queue / scheduler
   ▲                         │
   │ completion              ▼
Coherent memory ◄── DMA ── Local SRAM ──► Compute array
                         ▲       │
                         └ tiles ┘

Peak TOPS matters only when data reaches the array at the needed rate.

Metric graph

UTILIZATION BREAKDOWN

compute active   ██████████████████  58%
DMA wait         ██████████          31%
host sync        █████               15%
cache/coherency  ████                12%
idle bubbles     ███████             22%

Low utilization is usually a system integration problem.

Metrics and artifacts

• accelerator utilization

• DMA bandwidth

• kernel launch overhead

• coherency invalidation rate

Mini case study

NPU met TOPs target but end-to-end inference slow — DMA and weight fetch dominated. Architecture added on-chip SRAM tile and double-buffering.

Debug branches

• If util low, check launch overhead and host sync first.

• If BW high, examine weight layout and sparsity support.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.