Cache Organization and Access Path — Design Space Exploration

Design space exploration

For Cache Organization and Access Path, senior architects do not pick one answer — they map the design space, estimate metric movement, and choose based on product constraints.

Option A — conservative

• Conservative: helps lower risk

• Risk: less upside

• Validate with: baseline suite

Option B — balanced

• Balanced: helps good perf/watt

• Risk: may miss peak

• Validate with: multi-workload sweep

Option C — aggressive

• Aggressive: helps peak wins

• Risk: PPA/DV risk

• Validate with: stress suite

Option D — software-first

• Software-first: helps low silicon

• Risk: fragile

• Validate with: controlled apps

DESIGN SPACE — Cache Organization and Access Path
low risk -> balanced -> aggressive
with software-first as alternate axis

Common pitfalls

• Aggressive hardware before workload proof

• Balanced by habit without numbers

Architecture deep dive

Cache hierarchy trades area and power for AMAT and bandwidth.

Concept diagram

MEMORY HIERARCHY

Core
 ├─ L1I / L1D  (cycles: 1-4, tiny, latency critical)
 ├─ L2         (cycles: 8-20, private or cluster)
 ├─ LLC / SLC  (shared, bandwidth + coherency point)
 ├─ NoC        (queueing + arbitration)
 └─ DRAM/HBM   (large penalty, high energy)

AMAT = hit_time + miss_rate × miss_penalty
But senior analysis also asks: MLP, bandwidth, QoS, and tail latency.

Metric graph

MISS PENALTY WATERFALL

L1 hit          ██  3 cyc
L2 hit          ████████  12 cyc
LLC hit         ███████████████  32 cyc
DRAM miss       ████████████████████████████████████  180 cyc

Small MPKI can still dominate if miss penalty is huge.

Metrics and artifacts

• MPKI per level

• L2/L3 bandwidth utilization

• replacement policy stats

• prefetch accuracy

Mini case study

Doubling L2 size reduces capacity misses but IPC improves only 3% because conflict misses dominate a shared workload. Fix data layout and false sharing before more SRAM.

Debug branches

• If MPKI high but bandwidth low, footprint may exceed capacity.

• If bandwidth saturated, coherency or DMA may be the real limit.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.