Computer Architecture · All levels

PPA at System Level — Step-by-Step Walkthrough

Step-by-Step Walkthrough for PPA at System Level (SoC Architecture Tradeoffs).

Step-by-step analysis walkthrough

Follow this walkthrough when you own PPA at System Level in a performance review or architecture signoff meeting.

  1. Confirm workload and analysis tag.

  2. Open System-level PPA budget ledger and capture worst cluster.

  3. Classify bottleneck type.

  4. Map cluster to structure.

  5. List competing hypotheses.

  6. Run cheapest falsifying experiment.

  7. Estimate metric delta.

  8. Choose bounded change.

  9. List regression surfaces.

  10. Replay workloads.

  11. Write decision memo.

  12. Capture methodology guardrail.

Artifacts to collect

  • Workload list

  • PMU/trace config

  • Metric dashboard

  • Decision memo

Decision memo template

diagram
DECISION MEMO — PPA at System Level
metric:
hypothesis:
experiment:
decision:
validation:

Architecture deep dive

Chip architecture signoff is a negotiated PPA contract across teams.

Concept diagram

diagram
PPA NEGOTIATION MAP

Architecture target
   │
   ├─ Performance: IPC, latency, bandwidth, QoS
   ├─ Power: dynamic, leakage, thermal envelope
   ├─ Area: SRAM, logic, NoC links, floorplan
   ├─ Verification: state space, tests, formal complexity
   └─ PD: timing, placement, macro distance, routing channels

A staff architect makes the trade visible before it becomes a crisis.

Metric graph

diagram
PPA OPTION CHART

Option          Perf      Power     Area      Risk
A wider core    +++       ---       --        high
B better cache  ++        -         --        med
C SW locality   +         +         0         med
D NoC QoS       +         -         -         low

Pick based on product objective, not elegance.

Metrics and artifacts

  • PPA dashboard

  • floorplan distance budget

  • NoC BW matrix

  • verification closure status

Mini case study

CPU–memory macro distance violated latency budget — architecture accepted lower CPU frequency rather than respin floorplan one week before tapeout.

Debug branches

  • If PD pushes back, bring numeric latency/power models not opinions.

  • If signoff yellow, document owner, mitigation, and decision date.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.