Reset questions test ordering arguments: assertion is easy, deassertion is the hazard, and release order is the system argument. Speak the recovery and removal mechanism before naming any circuit.
Outline: Mechanism, assertion drives every flop to reset regardless of clock phase, but deassertion releases flops near a clock edge, risking recovery and removal violations that leave some flops in reset and others out. Pattern, a reset synchroniser releasing each domain synchronously. Reference: Why Deassertion Is the Hazard.
Outline: asynchronous assert into a two-flop chain in the destination clock, synchronous release at the chain output. Rules, no logic between the flops, the chain clocked by the domain it releases, reset in the synchroniser's own domain handled too. Reference: Reset Synchroniser Structure.
Outline: Assumption, the stated dependency: domain B needs domain A's clock and reset stable first. Mechanism, ordered release ranks with B held until A is out, checked as a reset-ordering violation otherwise. Evidence, the RDC structural report plus a reset-aware simulation of the ordered sequence. Reference: Release Order Across Domains.
Outline: reset-domain membership per register, asynchronous-deassertion paths without a synchroniser, reset crossings across clock domains, and ordering violations between sequenced resets. Each maps to intent rows, not just synchroniser instances. Reference: RDC Categories.
Outline: Two: a reset domain is defined by shared release behaviour, not by the net name. Crossings between the blocks need checking even though the source net is shared. This is the intent question interviewers use to test whether you read netlists or block diagrams.
Outline: No. Mechanism, release simulation samples some sequences at one corner; without intent the analysis had nothing to check against, so a clean report means nothing. Evidence required, reviewed reset intent plus re-run analysis plus the simulated sequences. Level 4 adds: say which sequences simulation cannot cover, mid-operation assertion and every power-up ordering.
Assertion is self-timed but deassertion races the clock, so only a synchronised release checked against written intent counts as evidence, never a passing simulation alone.