Single-bit crossings are the most-asked whiteboard topic because they expose mechanism thinking in two minutes. Speak each answer with the framework; the outlines below show the points a level-3 answer must hit.
Outline: Assumption, unrelated clocks. Mechanism, the first flop can resolve late; the second flop samples it after (nearly) a full destination period, so it almost always sees a settled value. Trade-off, two stages cost two cycles of latency; a third stage buys failure-rate margin, not correctness. Evidence, structural check for no logic between flops plus the resolution-time argument in Resolution Time and MTBF.
Outline: Assumption, asynchronous clocks, unknown phase. Mechanism, lost event: the pulse can fall entirely between two slow edges. Trade-off, direct capture is free and wrong. Evidence, a waveform showing the pulse between slow edges, as in Failure Modes. Level 4 names the mirror failure: duplicated events in the slow-to-fast direction.
Outline: toggle on each source event, two-flop synchronise the toggle, edge-detect in the destination. Rule, events must be spaced so the destination sees each toggle level: at least two destination periods apart in practice. Evidence, structural report plus an assertion that every toggle yields exactly one strobe. Reference: Toggle Synchronizer and Spacing and Rate Limits.
Outline: Mechanism, toggles merge and one event is lost, so the toggle scheme's assumption is violated. Pattern, a handshake or FIFO that applies back-pressure. Trade-off, acknowledgement latency and logic against guaranteed delivery at any spacing. Evidence, formal proof of no lost or duplicated events under any spacing.
Outline: Mechanism, the second flop samples a function of a possibly still-resolving node, so the settling argument collapses and downstream fanout can diverge. Verdict, defect, no waiver: re-register so nothing sits between the flops. Evidence, the structural check for logic between synchroniser flops, taught in No Logic Between Flops.
Outline: deterministic clocks at an exact multiple, one-cycle event pulses spaced several slow periods apart, a counter on destination strobes, print PASS only when every event produced exactly one strobe. The example below is complete and prints PASS under Icarus Verilog; keep it as your template for whiteboard-adjacent code questions.
// Complete, runnable toggle synchroniser testbench: prints PASS.
module tb;
reg clk_f = 0;
always #5 clk_f = ~clk_f; // 100 MHz source clock
reg clk_s = 0;
always #20 clk_s = ~clk_s; // 25 MHz destination clock
reg rst_f = 1, rst_s = 1;
reg pulse_f = 0, tog_f = 0;
reg s1 = 0, s2 = 0, s3 = 0;
wire got_s = s2 ^ s3;
integer got_count = 0;
always @(posedge clk_f)
if (rst_f) tog_f <= 0;
else if (pulse_f) tog_f <= ~tog_f;
always @(posedge clk_s)
if (rst_s) begin s1 <= 0; s2 <= 0; s3 <= 0; end
else begin s1 <= tog_f; s2 <= s1; s3 <= s2; end
always @(posedge clk_s)
if (!rst_s && got_s) got_count <= got_count + 1;
initial begin
#45 rst_f = 0; rst_s = 0;
#35 pulse_f = 1; #10 pulse_f = 0;
#120 pulse_f = 1; #10 pulse_f = 0;
#120 pulse_f = 1; #10 pulse_f = 0;
#200;
if (got_count == 3) $display("PASS: 3 events, 3 strobes");
else $display("FAIL: got_count=%0d, expected 3", got_count);
$finish;
end
endmoduleDrills 2 and 4: the lost event and its back-to-back variant. Both turn on the spacing assumption: the toggle scheme is correct only when events are spaced, and the handshake exists for when they are not.