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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
    • CDC/RDC Whiteboard Framework
    • CDC/RDC Framework Drills
      • Drill Set: Single Bit
      • Drill Set: Multi-Bit and FIFO
      • Drill Set: Reset and RDC
    • Scenario: Metastability Bug
    • Scenario: Metastability Escape in Silicon Bring-up
    • Scenario: Async FIFO Pointer Mismatch
    • Scenario: Waiver Debate
    • Scenario: RDC Waiver Under Tapeout Pressure
    • CDC/RDC Interview Q&A Bank
    • CDC/RDC Interview Q&A Bank (Expanded)
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹CDC/RDC Framework Drills
  1. Topics
  2. CDC & RDC
  3. CDC and RDC Interview Prep
  4. CDC/RDC Framework Drills
  5. Drill Set: Multi-Bit and FIFO

Part 10 · Interview Prep · All levels

Drill Set: Multi-Bit and FIFO

Six timed multi-bit, Gray code and FIFO drills with model answer outlines.

On this page

    Multi-bit questions test whether you reach for per-bit synchronisers out of habit. Every drill below punishes that reflex; speak the torn-bus mechanism first, then the pattern.

    Drill 1: an 8-bit counter crosses domains with one two-flop synchroniser per bit. Verdict?

    Outline: Mechanism, torn bus: bits settle at different times and the destination mixes old and new bits, producing values the counter never held. Verdict, defect. Pattern, Gray code, handshake, or FIFO depending on rate. Evidence, structural check flagging a multi-bit crossing without a protocol. Reference: Where Gray Fails for the boundary of the Gray answer.

    Drill 2: state the one-bit-change rule and where it breaks.

    Outline: consecutive Gray values differ in exactly one bit, so a sampled transition resolves to the old or the new value, never a third. Breaks when the source changes more than one step per destination sample, for non-power-of-two ranges handled naively, or when the Gray word reconverges with other logic. Reference: The One-Bit-Change Rule.

    Drill 3: two synchronised Gray pointers reconverge into an empty comparison. What is the risk?

    Outline: Mechanism, reconvergence: two separately synchronised paths rejoin, and skew between them can glitch the comparison. Pattern, compare full and empty in one domain each using the synchronised pointer, never combine two fresh crossings in one gate. Evidence, the structural reconvergence report. Reference: What Is Reconvergence.

    Drill 4: size an async FIFO from rate and latency.

    Outline: Assumption, stated write and read rates plus the round-trip latency of the full and empty feedback. Mechanism, depth must cover the bursts the reader cannot drain while the flags propagate. Trade-off, deeper costs area and empty latency; shallower risks overflow. Reference: Depth Sizing. Level 4 adds reset: pointers must release into a known empty state, per FIFO Reset and Tool Checks.

    Drill 5: full and empty each belong to one domain. Which one, and why?

    Outline: empty is generated in the read domain from the synchronised write pointer; full is generated in the write domain from the synchronised read pointer. Mechanism, each flag compares a local pointer against a synchronised copy, so no comparison ever mixes two crossing paths. Reference: Full and Empty.

    Drill 6: a slow control bus changes rarely and is read across the crossing. Cheapest safe pattern?

    Outline: qualified quasi-static capture: hold the bus stable, synchronise a valid pulse, capture the bus while held, per Qualified Capture. Trade-off, near-zero logic against a stability contract the source must honour. Evidence, constraints or assertions proving the bus is stable across the capture window, plus waiver hygiene from Constraints and Waiver Hygiene.

    Common pitfall

    Saying "Gray code" and stopping on drill 1. Gray code is a means, not a complete answer: the interviewer is waiting for the rate argument (one step per sample) and the comparison placement (full and empty each in one domain).

    Check yourself Drills 3 and 5 teach one shared principle. State it.

    Never combine two freshly crossed signals in one function: full and empty each compare a local pointer with one synchronised copy, in a single domain, so no gate ever sees two skews at once.

    Related topics

    • Next: Reset and RDC Drills

    • Gray pointers in signoff

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