VLSI DV Interview Puzzles · All levels

Intersect End-Time Mismatch

Property intent: both branches must match with the same start and same end using intersect. Timeline: C50 start=1 req=1, C51 gnt=1, C52 d1. Determine the verdict.

Puzzle

Difficulty: Hard · Puzzle 5 of 6 · Topic: Sequence Puzzles

Property intent: both branches must match with the same start and same end using intersect. Timeline: C50 start=1 req=1, C51 gnt=1, C52 done=1. Determine the verdict.

Code

systemverilog

property p_seq_intersect;
  @(posedge clk) start |-> ((req ##1 gnt) intersect (req ##2 done));
endproperty

Hint

Intersect is stricter than and: same start and same end cycle.

Step-by-step solution

diagram

1) Left branch ends at C51 (req ##1 gnt).
2) Right branch ends at C52 (req ##2 done).
3) End times differ by one cycle.
4) intersect therefore has no valid match.

Answer

Answer: FAIL - both branches start together, but they end on different cycles, violating intersect semantics.

Why candidates get it wrong

Candidates who memorize only logical intuition miss that intersect constrains temporal end alignment.

Interviewer follow-up

What minimal code change would make this puzzle pass while keeping intersect?

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