Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
      • Exact Delay Then Bounded Hold
      • Goto Repetition With Sparse Events
      • Nonconsecutive Repetition [=2]
      • Sequence and Operator
      • Intersect End-Time Mismatch
      • within and Alternative Windows
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
Loading lesson

‹Sequence Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Sequence Puzzles
  5. within and Alternative Windows

VLSI DV Interview Puzzles · All levels

within and Alternative Windows

Property intent: ack ##1 done must complete within either a 4-cycle or 5-cycle request window. Timeline: C60 start=1 req=1, C62 ack=1, C63 d1, C64 end_win=1. Determine the verdict.

On this page

    Puzzle

    Difficulty: Hard · Puzzle 6 of 6 · Topic: Sequence Puzzles

    Property intent: ack ##1 done must complete within either a 4-cycle or 5-cycle request window. Timeline: C60 start=1 req=1, C62 ack=1, C63 done=1, C64 end_win=1. Determine the verdict.

    Code

    design.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    sequence resp_seq;
      ack ##1 done;
    endsequence
    
    sequence win4;
      req ##[1:4] end_win;
    endsequence
    
    sequence win5;
      req ##[1:5] end_win;
    endsequence
    
    property p_within_or;
      @(posedge clk) start |-> (resp_seq within (win4 or win5));
    endproperty

    Hint

    Check containment of the full resp sequence, not just ack.

    Step-by-step solution

    Diagram
    1) start launches matching at C60.
    2) resp_seq spans C62 to C63.
    3) win4 can match as req at C60 and end_win at C64, spanning C60 to C64.
    4) resp_seq is fully contained inside that window; or is satisfied by win4 alone.

    Answer

    Answer: PASS - resp_seq is fully enclosed by a valid request window, so within succeeds via the win4 branch of the or composition.

    Why candidates get it wrong

    Engineers often evaluate only start alignment and forget that within requires full-sequence containment.

    Interviewer follow-up

    If done moved to C65 while end_win stayed at C64, what verdict would you expect?

    Related topics

    • Back to Sequence Puzzles

    • SVA Assertion Puzzles section

    Previous

    110 / 210

    Next: Implication Puzzles

    Up next

    Up nextImplication Puzzles

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Exact Delay Then Bounded Hold
    • Goto Repetition With Sparse Events
    • Nonconsecutive Repetition [=2]