Global routing estimates demand versus capacity and guides major route decisions. Detailed routing realizes geometry and vias under design rules. If global overflow remains unresolved, detailed routing converges slowly with repeated violations.
Stage: Routing
Primary risk if ignored: Ignoring convergence signals causes schedule slips and unstable late ECO loops.
Evidence artifact: section-specific report or map
1. Identify where Global and Detailed Routing Convergence sits in the PD flow
2. Name inputs consumed and outputs produced
3. State the metric that proves success or failure
4. Link to the next downstream stage that depends on this stepNarrate Global and Detailed Routing Convergence using metrics, not tool commands alone.
A senior engineer does not describe Global and Detailed Routing Convergence as a tool step. They explain what physical assumption changed, which report becomes trustworthy after that change, and which downstream owner can now make a decision.
Which stage of the database is valid: pre-CTS, post-CTS, post-route, post-fill, or final signoff.
Which approximation is still present: estimated RC, ideal clock, abstracted macro, vectorless power, or waived PV rule.
Which downstream result depends on this mechanism: Timing closure and PV signoff rely on robust route legality..
You can point to Routing closure dashboard before proposing a fix.
You can separate a local symptom from a systematic methodology issue.
You can explain why the fix is reversible, bounded, and cheaper than the alternatives.
Routing decides whether the placed design is manufacturable and extractable.
global route overflow by layer and region
detailed route DRC/DRV summary grouped by rule
antenna report: gate area, metal area, ratio, suggested diode
post-route extraction delta on critical nets
Detailed route completes with 4,000 spacing violations around a macro channel. The design is not 'routed'. Cluster by rule and region, fix the channel or layer plan, then re-route locally.
If antenna violations cluster on long lower-metal routes, jump to upper metal earlier or insert diode cells.
If via violations dominate, inspect via arrays and preferred via stacks, especially on power transitions.
If crosstalk worsens timing, space, shield, or layer-promote the victim nets.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Routing decides whether the placed design is manufacturable and extractable. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.