Core concepts

APB: simple, slow, correct for control

APB (Advanced Peripheral Bus) is a non-pipelined, low-complexity bus for register access. Every transfer takes minimum 2 cycles: SETUP (PSEL=1, PENABLE=0) then ACCESS (PSEL=1, PENABLE=1). The slave stretches with PREADY=0.

APB has no bursts, no outstanding transactions, no separate read/write channels. This simplicity makes it ideal for GPIO, timers, and config registers where latency doesn't matter but area and power do.

APB STATE MACHINE

IDLE --(transfer)--> SETUP --(always)--> ACCESS
 ^                                          |
 +--------(pready=1, no more)----------------+
                    |
              (pready=1, more) --> SETUP

AHB variants: pipelining without AXI channels

AHB overlaps address and data phases: while data for transfer N is on the bus, address for transfer N+1 is presented. HREADY=0 stalls the entire pipeline.

Keep the variant explicit. AHB-Lite supports pipelined transfers and bursts, with OKAY/ERROR responses; it does not support SPLIT or RETRY. Those responses belong to the older full AHB protocol. An AHB-Lite target needing more time extends the data phase using HREADY. Both simple new subsystems and existing IP can use AHB-Lite; decide from latency, bandwidth, area and integration requirements.

• AHB default slave responds with ERROR if address not decoded.

• HTRANS: IDLE, BUSY, NONSEQ, SEQ encodes burst position.

• AHB-to-AXI bridges are common integration points — review burst conversion.

Key takeaways

• AHB default slave responds with ERROR if address not decoded.

• HTRANS: IDLE, BUSY, NONSEQ, SEQ encodes burst position.

• AHB-to-AXI bridges are common integration points — review burst conversion.