Primary debug scenario

Symptom: Firmware write to GPIO register hangs. PREADY never asserts. Simulation passes with backdoor access.

Triage steps

1. Check PSEL decode — does the address hit the GPIO block?

2. Verify clock and reset to the APB slave — is it held in reset?

3. Check PENABLE sequencing — SETUP must precede ACCESS.

4. If bridge from AXI: verify AW/W channel completes and APB side starts.

5. Waveform: PSEL, PENABLE, PADDR, PREADY on same clock domain.

Common pitfalls

• Accessing APB peripheral before reset release completes.

• Address map mismatch between firmware header and RTL decode.

• Using APB for high-frequency register polling.