AXI splits reads and writes completely. Write address (AW) and write data (W) are separate channels — W beats can arrive before or after AW depending on implementation. Write response (B) confirms completion. Read address (AR) and read data (R) are similarly independent.
This independence is why AXI achieves high throughput: a master can pipeline reads while writes are in flight, and multiple outstanding transactions hide DRAM latency.
AXI CHANNELS
WRITE: AW (addr) ─┐
W (data) ─┼─> slave ──> B (resp)
READ: AR (addr) ───> slave ──> R (data+resp)
Each channel: independent valid/ready handshakeAXI4 AW and W offers and handshakes are independent in time: W may precede AW. Associate W bursts with AW request order; AXI4 has no WID and does not allow write-data interleaving between bursts. WLAST qualifies the final beat, counted only on WVALID && WREADY. BVALID follows acceptance of both AW and the final W beat, with BID matching AWID. Read beats within a burst are ordered; same-ID read bursts return in AR order, while different IDs may reorder or interleave.
For AXI4, bytes per transfer are 2^AxSIZE and cannot exceed either agent's data-bus width. Narrow transfers are legal; supported unaligned transfers require consistent address and byte-lane handling. AxLEN encodes beats minus one. FIXED, INCR and WRAP have different address rules; WRAP starts must be transfer-size aligned, and bursts must not cross a 4 KiB boundary. Check Arm IHI 0022H A3.4 rather than imposing full-bus-width alignment on every access.
Illustrative byte-lane exercise: on a 32-bit bus, a single write with AWADDR=0x1002, AWSIZE=1 and AWLEN=0 addresses two bytes. WSTRB=0b1100 enables lanes 2 and 3 for addresses 0x1002 and 0x1003. AWSIZE=3 would be invalid on this bus because it requests an eight-byte transfer. Separately, an aligned two-beat INCR burst starting at 0x0FFC with four-byte beats would cross into the next 4 KiB region and must be split into separate legal requests by the requester/adaptation layer.
Early W data needs buffering or backpressure until associated AW context exists. W bursts follow AW order across IDs and cannot interleave; gaps/stalls between beats are legal. Never require AWREADY before presenting WVALID.
WSTRB indicates which byte lanes are valid — don't ignore on sub-word writes.
AxCACHE and AxPROT affect system behavior — bridges must propagate them.
Early W data needs buffering or backpressure until associated AW context exists. W bursts follow AW order across IDs and cannot interleave; gaps/stalls between beats are legal. Never require AWREADY before presenting WVALID.
WSTRB indicates which byte lanes are valid — don't ignore on sub-word writes.
AxCACHE and AxPROT affect system behavior — bridges must propagate them.