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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
    • APB & AHB Basics
    • AXI Channels & Transfers
      • AXI Channels & Transfers: Concepts
      • AXI Channels & Transfers: Integration
      • AXI Channels & Transfers: Debug
      • AXI Channels & Transfers: Interview
    • AXI-Lite & AXI-Stream
    • AMBA Integration Debug
    • AMBA Family (APB / AHB / AXI): Tricky Q&A
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←AXI Channels & Transfers
  1. Topics
  2. Bus Protocols
  3. AMBA Family (APB / AHB / AXI)
  4. AXI Channels & Transfers
  5. AXI Channels & Transfers: Debug
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    Interface ProtocolsAll levels

    AXI Channels & Transfers: Debug

    Debug for AXI Channels & Transfers.

    Primary debug scenario

    Symptom: Write burst hangs. AW channel completes. W beats stop after 2 of 4. B never returns.

    Triage steps

    1. Check W channel: are remaining beats being sent? Is WVALID stuck low?

    2. Verify WLAST on the correct beat — missing WLAST stalls the slave forever.

    3. Check if a width converter is splitting the burst and losing count.

    4. Verify AWLEN matches actual W beat count.

    5. If interconnect: check if W beats route to the correct slave port.

    Common pitfalls

    • Checking only AW without following W channel completion.

    • WLAST missing or on wrong beat.

    • Bridge dropping W beats during width conversion.

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    See also

    • AXI Channels & Transfers: Concepts