Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
    • ACE Coherent Transactions
    • Snoop & Cache Maintenance
    • CHI Topology Basics
      • CHI Topology Basics: Concepts
      • CHI Topology Basics: Integration
      • CHI Topology Basics: Debug
      • CHI Topology Basics: Interview
    • Coherence Fabric Debug
    • Coherence Fabrics (ACE / CHI): Tricky Q&A
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
Loading lesson

←CHI Topology Basics
  1. Topics
  2. Bus Protocols
  3. Coherence Fabrics (ACE / CHI)
  4. CHI Topology Basics
  5. CHI Topology Basics: Concepts
On this page

    Interface ProtocolsAll levels

    CHI Topology Basics: Concepts

    Concepts for CHI Topology Basics.

    Core concepts

    CHI node types and message flows

    In the simplified coherent path here, a Request Node initiates accesses, a coherent Home Node coordinates coherence for its assigned addresses, and a Subordinate Node provides downstream service. CHI defines different coherent and non-coherent node types; these three labels alone do not specify every capability. Arm IHI 0050 Issue H B1.6 permits an HN-F to include a directory or snoop filter rather than requiring one.

    CHI separates REQ (request), RSP (response), DAT (data) and SNP (snoop) roles. That separation supports concurrency, but the protocol, network and buffering design must still preserve their dependency rules. Separate channels alone do not prove absence of deadlock, livelock or starvation.

    Diagram
    CHI TOPOLOGY (simplified)
    
    RN (CPU0) ----\
    RN (CPU1) -----+--> HN (coherent home) ----> SN (DRAM)
    RN (GPU)  ----/        |
                       SNP network to peer RNs

    Directory-based coherency

    A directory or snoop filter can reduce unnecessary snoops using conservative knowledge of which caches may hold a line. Its representation, capacity and handling of missing information are implementation choices. Do not equate CHI with mandatory exact-directory tracking or assume ACE always broadcasts. There is no universal eight-core or 32-core protocol scaling threshold; compare the actual traffic and resources.

    In AMBA CHI Issue H request retry, a Completer that cannot accept an eligible first request can return RetryAck and later PCrdGrant for the required Protocol Credit. The Requester must wait for both before resending with AllowRetry deasserted and the granted PCrdType; the credited retry is guaranteed acceptance under the protocol rules. A high RetryAck rate shows admission/resource pressure at a Completer or path, but does not by itself identify a home-node compute bottleneck.

    • Home placement and address distribution affect locality and hotspots; evaluate the selected topology.

    • Directory representation trades storage, filtering precision and fallback traffic; bit-vector width is not the only possible encoding.

    • Distinguish CHI channel/link flow control from implementation-specific NoC virtual channels and buffer pools.

    Key takeaways

    • Home placement and address distribution affect locality and hotspots; evaluate the selected topology.

    • Directory representation trades storage, filtering precision and fallback traffic; bit-vector width is not the only possible encoding.

    • Distinguish CHI channel/link flow control from implementation-specific NoC virtual channels and buffer pools.

    Previous

    55 / 154

    Next: CHI Topology Basics: Integration

    Up next

    Up nextCHI Topology Basics: Integration

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • CHI Topology Basics: Debug
    • CHI Topology Basics: Interview