Every peripheral has a contract: register map (offsets, reset values, access width), interrupt spec (level/edge, polarity, clear mechanism), clock/reset requirements, and DMA interface (if any). Firmware, RTL, and verification must share one source of truth.
Most peripheral bugs are mismatches: firmware writes offset 0x04 but RTL decodes 0x08. Driver expects edge-triggered IRQ but hardware is level. DMA starts before peripheral is out of reset.
Register spec is the contract — version it with RTL and driver.
Reset value audit: does the peripheral work with just reset (no firmware)?
Interrupt storm: level IRQ not cleared → infinite interrupt loop.
Register spec is the contract — version it with RTL and driver.
Reset value audit: does the peripheral work with just reset (no firmware)?
Interrupt storm: level IRQ not cleared → infinite interrupt loop.