MAC handles Ethernet frames: preamble, destination/source MAC, type/length, payload, FCS (CRC). Flow control via pause frames. VLAN tagging and checksum offload are MAC features.
PCS (Physical Coding Sublayer) handles the selected Ethernet mode's coding and synchronisation. For example, IEEE 802.3 Clause 49 defines 10GBASE-R 64b/66b coding. Do not treat this as the encoding of every 10G-or-faster PHY; the medium, mode and generation matter. Interpret PCS error counters with that mode's definitions.
PHY (SerDes) handles electrical signaling: equalization, auto-negotiation (for copper), link status.
ETHERNET STACK
App/Driver --> MAC (frames, CRC) --> PCS (encode) --> PHY (SerDes) --> cable/fiber
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packet counters block lock link status
FCS errors alignment eye marginAn RX FCS/CRC mismatch means the checked frame does not match its checksum. It can direct investigation towards the receive path, but it does not alone prove a wire or board fault: compare PHY/PCS errors, interface timing, MAC configuration and observation boundaries. Likewise, inspect the documented meanings of frame-error and TX-drop counters before assigning causes.
Link up with rising FCS errors warrants correlating MAC, PCS and PHY evidence over the same interval. Electrical margin is one candidate; interface timing, mode/configuration, reset/clock events and the counter's observation point remain candidates too.
Pause frames: receiver telling sender to slow down (flow control).
Frames above the path's standard payload/MTU expectation require compatible endpoint and network-path configuration; state whether a quoted size is payload, MTU or full frame.
PTP timestamping: hardware capture at PHY/MAC boundary.
Pause frames: receiver telling sender to slow down (flow control).
Frames above the path's standard payload/MTU expectation require compatible endpoint and network-path configuration; state whether a quoted size is payload, MTU or full frame.
PTP timestamping: hardware capture at PHY/MAC boundary.