MAC is digital RTL. PHY is analog SerDes macro. The interface between them (XGMII, XLGMII, etc.) has strict timing. RGMII (1G) uses DDR signaling that is board-sensitive.
RGMII delay: PCB trace length matching between MAC and PHY chip.
SerDes reference clock quality affects BER.
MAC address filtering: promiscuous mode for debug.