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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
      • USB Link & Packet Model: Concepts
      • USB Link & Packet Model: Integration
      • USB Link & Packet Model: Debug
      • USB Link & Packet Model: Interview
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←USB Link & Packet Model
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. USB Link & Packet Model
  5. USB Link & Packet Model: Concepts
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    Interface ProtocolsAll levels

    USB Link & Packet Model: Concepts

    Concepts for USB Link & Packet Model.

    Core concepts

    USB topology and enumeration

    Host controller initiates everything. Devices attach to ports (root or hub). Enumeration: host assigns address, reads descriptors (device, configuration, interface, endpoint), selects configuration.

    Endpoints are the data pipes: bulk (reliable, best-effort bandwidth), interrupt (periodic, small), isochronous (time-bound, no retry). Each endpoint has max packet size and polling interval.

    Diagram
    USB DATA FLOW
    
    Host Controller --> Hub --> Device
                    |            |
               schedule         endpoints
               transfers        EP0: control
                                EP1: bulk IN
                                EP2: interrupt

    Link states and packets

    For USB 2.0 control, bulk and interrupt transfers, transactions use token, optional data and applicable handshake packets. Isochronous transfers do not use a transaction-level retry handshake. NAK can report temporary inability on applicable transfers; STALL reports a halted or unsupported endpoint condition whose recovery depends on the transfer and host-stack contract.

    USB 3.x has revision-specific link training, link states and packet mechanisms rather than reusing the USB 2.0 transaction model. Treat PCIe LTSSM only as a layering analogy, not as the USB state machine, and name the USB revision when discussing recovery or streams.

    For USB 2.0 timing, full-speed SOF packets mark 1 ms frames; high-speed SOF packets mark 125 µs microframes, eight per millisecond. At high speed, a 1 ms interval therefore spans eight microframes, not one. This is the scheduling timebase, not a promise that every endpoint transfers in every microframe: service depends on transfer type, endpoint configuration and the host schedule.

    • SOF (Start of Frame): 1 ms at full speed, 125 µs per microframe at high speed; keep speed and endpoint service interval distinct.

    • Packet-size limits depend on both speed and transfer type; do not apply a bulk-endpoint table to interrupt or isochronous endpoints.

    • ZLP (zero-length packet) marks end of some transfers.

    Key takeaways

    • SOF (Start of Frame): 1 ms at full speed, 125 µs per microframe at high speed; keep speed and endpoint service interval distinct.

    • Packet-size limits depend on both speed and transfer type; do not apply a bulk-endpoint table to interrupt or isochronous endpoints.

    • ZLP (zero-length packet) marks end of some transfers.

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    Next: USB Link & Packet Model: Integration

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    See also

    • USB Link & Packet Model: Debug
    • USB Link & Packet Model: Interview