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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
      • USB Link & Packet Model: Concepts
      • USB Link & Packet Model: Integration
      • USB Link & Packet Model: Debug
      • USB Link & Packet Model: Interview
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←USB Link & Packet Model
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. USB Link & Packet Model
  5. USB Link & Packet Model: Debug
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    Interface ProtocolsAll levels

    USB Link & Packet Model: Debug

    Debug for USB Link & Packet Model.

    Primary debug scenario

    Symptom: USB device not enumerated. PHY shows device attach detect. No USB traffic.

    Triage steps

    1. Check device controller clock and reset.

    2. Verify PHY reference clock and power.

    3. Scope D+/D- for chirp sequence (HS negotiation).

    4. Check if device firmware is running and responding to setup packets.

    5. USB analyzer: any activity on the bus at all?

    Common pitfalls

    • Descriptor mismatch: firmware reports capabilities silicon doesn't have.

    • Missing pull-up on D+ (FS) or D- (LS) for device detect.

    • Rewriting driver before checking PHY and device firmware.

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    See also

    • USB Link & Packet Model: Concepts