CXL memory can add capacity with latency and bandwidth determined by topology, link, device media, interleaving and load. It may be slower than a given local-memory path, but that is a platform measurement rather than a universal ordering. Placement/tiering is one possible software policy, not a mandatory hot/warm split. Cache-capable devices still need a defined coherence, ownership and synchronisation domain.
CXL switch enables multi-device topologies — each port trains independently.
CXL 2.0 introduced switched memory pooling: capacity can be assigned to different hosts without implying simultaneous coherent sharing of the same location. CXL 3.0 adds memory-sharing and expanded fabric capabilities; state the selected revision before relying on them.
Security: CXL memory regions need platform-appropriate discovery, isolation, access-control, integrity and lifecycle policy; do not reduce system memory semantics to MMIO.