Primary debug scenario

Symptom: Endpoint enumerates at x1 Gen3 instead of expected x4 Gen4. Same chip works on eval board.

Triage steps

1. Read LTSSM state history — where did width negotiation fail?

2. Per-lane margin report: which lane(s) failed EQ?

3. Compare package/board SI between eval and product.

4. Check if retimer or switch in path has independent training issues.

5. Compare physical margin, configured speed/width limits, reset and firmware settings before assigning the cause.

Common pitfalls

• Blaming software enumeration when PHY margin is the cause.

• Skipping LTSSM history and lane margin reports.

• Ignoring package/board differences between eval and product.