Start from the failure symptom. Identify the interface. Load waveform with protocol-relevant signals (not every signal in the design). Annotate transaction boundaries using VIP monitor or manual trace.
Scroll backward from the failure to find the earliest observed point where progress stopped or behaviour diverged from the stated expectation. The timeout 1000 cycles later is an observation; the causal dependency may begin earlier or outside the captured boundary.
Signal grouping: one group per channel (AR, AW, W, R, B for AXI).
Marker: tag the failing transaction's ID and timestamp.
Compare failing vs passing waveform side-by-side.
Waveform shows signals. VIP monitor shows transactions. Firmware log shows software actions. Analyzer shows external protocol view. Align timestamps across all views for the same transaction.
A signal-level view without transaction context is guesswork. A transaction log without signal correlation can't find the RTL bug.
Export VIP monitor to CSV — overlay with waveform markers.
Simulation: $display or transaction recording at key points.
Silicon: logic analyzer on external pins + on-chip trace buffer.
Signal grouping: one group per channel (AR, AW, W, R, B for AXI).
Marker: tag the failing transaction's ID and timestamp.
Compare failing vs passing waveform side-by-side.