Interface Protocols · All levels

Protocol Waveform Debug: Interview Drills

Interview Drills for Protocol Waveform Debug.

Interview drills

Interview Drills for Protocol Waveform Debug focuses on debug turnaround time, root-cause classification, rerun pass rate. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram
PROMPT
You see debug turnaround time, root-cause classification, rerun pass rate on Protocol Waveform Debug. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains waveform debug reconstructs transaction intent from signals, monitors, logs, and spec rules in timestamp order.
3. Requests annotated waveform, transaction timeline, root-cause note.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

Waveform debug reconstruction

diagram
RECONSTRUCT INTENT FROM SIGNALS

step 1: find first anomaly timestamp (T0)
step 2: scroll BACK to the request that started it
step 3: annotate id/addr on every related signal
step 4: mark where progress should have happened but did not
step 5: compare with the spec timing for that exact transaction

T-2   T-1   T0(bad)   T+1
 |     |      |         |
req  grant  (no resp)  timeout
        ^ root cause lives here, not at the timeout

Root-cause tree to narrate

diagram
ROOT-CAUSE TREE — Protocol Waveform Debug

debug turnaround time, root-cause classification, rerun pass rate looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

Concept diagram

diagram
VERIFICATION CLOSURE LOOP

spec clause -> test -> assertion -> coverage -> waiver -> signoff
                  ^                           |
                  +--------- gap found --------+

Metric graph

diagram
COVERAGE vs ESCAPE RATE

escapes
  |*
  | *
  |  *
  |   **  <- knee: more random helps
  |     ****
  +----------------> constrained-random depth

Metrics and artifacts to collect

  • compliance pass rate

  • coverage closure

  • scoreboard mismatch rate

  • assertion fire count

  • waiver log

Mini case study

Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

Debug branches

  • If VIP pass but silicon fail, check integration assumptions.

  • If scoreboard noisy, fix key (ID+port+addr).

  • If coverage plateau, add compliance gap analysis not more repeats.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

  • Connect every protocol claim to a transaction identity and measurable metric.

  • Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

  • Debugging timeouts without finding the first bad transaction.

  • Quoting peak bus width without payload efficiency and retry overhead.

  • Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.