Follow this when you own Protocol Waveform Debug in a protocol review or bring-up war room.
State expected transaction in plain language (who initiates, what completes).
Draw layer stack and mark clock/reset boundaries.
List channels: request, data, response, snoop, credit, or lane.
Tag ID/address/endpoint on the failing run.
Find first cycle where progress stops or semantics change.
Check bridge: width, ID remap, burst, ordering attributes.
Check flow control: ready, credit, FIFO, link state.
Check firmware/register mode vs hardware capability.
Build minimal replay; confirm legal vs illegal per spec.
Estimate metric delta from proposed fix.
Run compliance + product traffic regression matrix.
Write signoff memo with owners and artifacts attached.
annotated waveform, transaction timeline, root-cause note
VIP transaction log
Waveform with annotations
Spec clause reference
Regression manifest
PROTOCOL DECISION MEMO — Protocol Waveform Debug
metric:
transaction id:
layer:
hypothesis:
experiment:
fix:
validation:
owners: debug lead, verification owner, RTL ownerRECONSTRUCT INTENT FROM SIGNALS
step 1: find first anomaly timestamp (T0)
step 2: scroll BACK to the request that started it
step 3: annotate id/addr on every related signal
step 4: mark where progress should have happened but did not
step 5: compare with the spec timing for that exact transaction
T-2 T-1 T0(bad) T+1
| | | |
req grant (no resp) timeout
^ root cause lives here, not at the timeoutVerification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.
VERIFICATION CLOSURE LOOP
spec clause -> test -> assertion -> coverage -> waiver -> signoff
^ |
+--------- gap found --------+COVERAGE vs ESCAPE RATE
escapes
|*
| *
| *
| ** <- knee: more random helps
| ****
+----------------> constrained-random depthcompliance pass rate
coverage closure
scoreboard mismatch rate
assertion fire count
waiver log
Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.
If VIP pass but silicon fail, check integration assumptions.
If scoreboard noisy, fix key (ID+port+addr).
If coverage plateau, add compliance gap analysis not more repeats.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Re-read Protocol Waveform Debug against one concrete product workload, not a synthetic directed test.
waveform debug reconstructs transaction intent from signals, monitors, logs, and spec rules in timestamp order.
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