Every item on the checklist is a property of one part of the reset tree. Draw the tree first, then review it part by part.
Read it top to bottom, from the reset sources to the flops they clear.
Sources: every box at the top is documented, and the watchdog and software resets follow the same rules as the pin.
Controller: it owns the release order, so the sequencer test and the peers-alive assertion check this box.
Synchronisers: one per domain, released synchronously, with recovery and removal checked by STA. No combinational logic on these nets.
The crossing arrow: each one is listed by the RDC tool and has isolation, protocol tolerance or a coordinated reset.
Check | How |
|---|---|
Every reset domain and its source are documented, with the clocks it serves | Reset tree document; reset structure report from the RDC/lint tool |
Every asynchronous reset is released synchronously in its own domain | Reset synchroniser per domain; structural check |
Every signal crossing from reset domain A to B is listed | RDC tool report |
For each crossing: isolation, protocol tolerance, or coordinated reset | Review of the report; waivers explained |
Data buses that cross are not reset (or are marked invalid while in reset) | Code review; lint |
A reset event during any transfer leaves the crossing in a legal idle state | Randomised reset tests (as in the first lesson) |
Release order is defined and verified | Reset sequencer test; assertion that peers are alive before traffic |
Recovery/removal passes on every asynchronous reset release at all corners | STA, including reset paths |
No combinational logic on asynchronous reset nets except clean muxes for test | Structural reset check |
Software reset and watchdog paths follow the same rules | Review the reset sources |
Some tool violations are acceptable, such as an isolated receiver or a reset-value leak the receiver ignores. Each needs a waiver with a reason.
Someone other than the RTL author reviews the list. It is re-run on every reset-structure change.
Simulation: randomised reset during traffic, release order. Static: reset structure and synchronisers, crossing list, combinational logic on reset nets, recovery/removal (STA).