STA Mastery · All levels

Clock Definition & Uncertainty: Interview Drills

Interview Drills for Clock Definition & Uncertainty.

Interview drills

Interview Drills for Clock Definition & Uncertainty focuses on WNS/TNS on clocked paths, clock skew reports, uncertainty budget. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

diagram

PROMPT
You see WNS/TNS on clocked paths, clock skew reports, uncertainty budget on Clock Definition & Uncertainty. Walk through root cause and fix.

STRONG ANSWER
1. Names corner/mode/view and path group.
2. Explains SDC clocks define launch and capture time bases; uncertainty and skew model timing margin consumed before data-path delay is evaluated.
3. Requests report_clock, clock tree report, SDC clock block, skew histogram.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to upsizing cells, widening routes, or blaming tools without reading constraints and path delay.

Diagram to draw on the whiteboard

Launch vs capture clock domains

diagram

SETUP CHECK (simplified)

launch clock edge ----> data propagates through logic ----> arrives at capture FF
                                                              |
capture clock edge -----------------------------------------> required time
                                                              |
slack = required_time - arrival_time  (setup)

Hold is the reverse inequality: data must stay stable after capture edge.

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — Clock Definition & Uncertainty

WNS/TNS on clocked paths, clock skew reports, uncertainty budget looks wrong
        |
   same netlist tag?
     /        \
   no          yes
   |            |
 view/SDC     real path or
 mismatch     constraint bug
 /    \           |
lib   SPEF    delay breakdown
diff  diff    cell vs net

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

clock report
uncertainty budget
IO delay coverage
exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Principal STA review addendum

SDC clocks define launch and capture time bases; uncertainty and skew model timing margin consumed before data-path delay is evaluated.

Metric: WNS/TNS on clocked paths, clock skew reports, uncertainty budget

Practice this lesson