STA Mastery · All levels

Clock Definition & Uncertainty: Mechanism

Mechanism for Clock Definition & Uncertainty.

Mechanism to understand

Mechanism for Clock Definition & Uncertainty focuses on WNS/TNS on clocked paths, clock skew reports, uncertainty budget. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

SDC clocks define launch and capture time bases; uncertainty and skew model timing margin consumed before data-path delay is evaluated. Think of STA as a signed contract between constraints, parasitics, and implementation — slack is the measurable outcome.

Identify launch and capture clocks on the failing path.
Identify path group: reg2reg, in2reg, reg2out, or async.
Identify whether setup, hold, or both fail in the scenario.

Layered view

diagram

STA CLOSURE FLOW — Clock Definition & Uncertainty

constraints (SDC)
        |
        v
timing graph (cell + net delays)
        |
        v
MMMC scenarios (corner x mode x view)
        |
        v
variation + SI adjustments
        |
        v
slack (WNS/TNS) -> ECO -> regression

Debug rule: always state corner, mode, view, and database tag with slack.

Launch vs capture clock domains

diagram

SETUP CHECK (simplified)

launch clock edge ----> data propagates through logic ----> arrives at capture FF
                                                              |
capture clock edge -----------------------------------------> required time
                                                              |
slack = required_time - arrival_time  (setup)

Hold is the reverse inequality: data must stay stable after capture edge.

Uncertainty budget stack

diagram

CLOCK UNCERTAINTY BUDGET

period
  |-- clock skew (CTS)
  |-- jitter (source + PLL)
  |-- uncertainty (SDC margin)
  |-- useful skew (if any)
  = effective capture window for data

If uncertainty is too small -> false optimism.
If too large -> wasted timing margin.

Layer responsibilities

diagram

STA OWNERSHIP LAYERS — Clock Definition & Uncertainty

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

clock report
uncertainty budget
IO delay coverage
exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Mechanism deep dive

SDC clocks define launch and capture time bases; uncertainty and skew model timing margin consumed before data-path delay is evaluated.

Practice this lesson