STA Mastery · All levels
Exceptions & Audit Policy: Design Space
Design Space for Exceptions & Audit Policy.
Design space exploration
For Exceptions & Audit Policy, closure options trade margin, schedule, and regression risk.
Option A — conservative
Conservative margin: helps safe signoff
Risk: over-pessimism, area/power
Validate with: first silicon
Option B — balanced
Balanced derate: helps reasonable margin
Risk: needs approval
Validate with: mature node
Option C — aggressive ECO
Aggressive ECO: helps fast WNS gain
Risk: hold/SI regressions
Validate with: late schedule
Option D — RTL restructure
RTL restructure: helps structural fix
Risk: schedule hit
Validate with: chronic paths
DESIGN SPACE — Exceptions & Audit Policy
margin <-> performance <-> schedule
pick based on false path count, multicycle path audit rate, exception waiver backlog on product scenariosDesign pitfalls
ECO without regression matrix
Constraint change without audit
Tradeoff curve
BEFORE / AFTER ECO — Exceptions & Audit Policy
WNS (ps)
0 | --- target
-50 | ● regressed
-80 | ● before ECO
-20 | ● after ECO
+-------------------------------> ECO iteration
Prove setup AND hold moved safely.STA deep dive
SDC quality determines whether STA measures reality or fiction.
Concept diagram
SDC FLOW
RTL clocks -> create_clock / generated_clock
board -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis -> report_timingMetric graph
CONSTRAINT QUALITY
audited exceptions ████████████████ good
stale IO delays ██████ risk
missing gen clock ████ high escapeReports and artifacts
clock report
uncertainty budget
IO delay coverage
exception audit log
Mini case study
1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.
Debug branches
Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly
Senior review question
Ask: what corner/mode/view proves this topic is closed or failing?
Key takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.
Principal STA review addendum
Timing exceptions remove pessimism only when justified; bad exceptions hide real paths and are a top signoff escape vector.
Metric: false path count, multicycle path audit rate, exception waiver backlog