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Exceptions & Audit Policy: Worked Example

Worked Example for Exceptions & Audit Policy.

Worked example

Worked Example for Exceptions & Audit Policy focuses on false path count, multicycle path audit rate, exception waiver backlog. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

A signoff run shows false path count, multicycle path audit rate, exception waiver backlog. The first review mistake is to blame implementation without checking constraints. A better review starts by pinning one critical path, proving where slack was lost, and checking whether the SDC rule is correct for Exceptions & Audit Policy.

Sequence under inspection

diagram
TIMING PATH — Exceptions & Audit Policy

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: false path count, multicycle path audit rate, exception waiver backlog

Exception decision tree

diagram
PATH FAILING TIMING
        |
   physically impossible?
     /        \
   yes         no
    |           |
 false_path   multicycle?
 (documented)   /     \
              yes      no
               |        |
          set_multicycle  fix RTL/PD
  1. Capture report_timing and the relevant SDC excerpt.

  2. Tag corner, mode, view, and path group.

  3. Find the first cell or net that dominates critical delay.

  4. Compare against exception report, constraint audit log, waiver manifest.

  5. Choose one reversible ECO and write the regression matrix before editing netlist or constraints.

Did the fix work?

diagram
BEFORE / AFTER ECO — Exceptions & Audit Policy

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram
SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram
CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

  • clock report

  • uncertainty budget

  • IO delay coverage

  • exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

  • Diff SDC before ECO

  • Validate clocks on failing path

  • Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

  • State corner, mode, view, and database tag with every slack claim.

  • Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

  • Comparing STA runs with different SPEF or SDC tags.

  • Broad false_path to green-wash violations.

  • Setup-only ECO without hold check.

Principal STA review addendum

Timing exceptions remove pessimism only when justified; bad exceptions hide real paths and are a top signoff escape vector.

Metric: false path count, multicycle path audit rate, exception waiver backlog