Part 2 · Phases & Lifecycle · Intermediate

check/report Debug: False Passes and Teardown Gaps

Triage patterns for silent false passes, missing extract data, conflicting RESULT banners, and final_phase resource leaks.

Common failure modes

False PASS with functional bugs

  1. check_phase never raised uvm_error despite scoreboard mismatches — compare ran only in scoreboard but mismatch_count not copied in extract.

  2. report_phase printed PASS from a local flag, ignoring report server errors.

  3. Warnings treated as pass — only ERROR and FATAL count.

False FAIL with healthy DUT

  1. Zero-transaction guard tripped because objection dropped too early.

  2. Coverage goal read before extract_phase populated cov_pct.

  3. Duplicate uvm_error from env and test for the same condition.

diagram
[PHASE][UVM] cleanup debug flow

symptom: PASS but DUT wrong
   verify scoreboard mismatch_count in extract log
   verify check_phase uvm_error paths
   grep UVM_ERROR count vs RESULT banner

symptom: FAIL with traffic visible
   check zero-txn guard threshold
   verify exp_count vs act_count semantics
   read extract_phase logged totals

Debug toolkit

  • +UVM_PHASE_TRACE — confirm extract/check/report/final order.

  • Log extracted totals at UVM_MEDIUM in extract_phase.

  • Log check_phase entry with all invariant inputs.

  • Compare RESULT banner against get_severity_count.

systemverilog
function void check_phase(uvm_phase phase);
  super.check_phase(phase);
  `uvm_info("CHECK_DBG", $sformatf(
    "inputs: txns=%0d mismatches=%0d cov=%.1f",
    act_count, mismatches, cov_pct), UVM_MEDIUM)
  // ... invariant checks ...
endfunction

Key takeaways

  • False passes usually mean extract skipped or report ignored error count.

  • Log invariant inputs in check_phase for one-run diagnosis.

  • +UVM_PHASE_TRACE confirms cleanup phase ordering.

Common pitfalls

  • Debugging with waveforms when the issue is missing extract super call.

  • Removing zero-txn guard instead of fixing objection leak.

  • Closing log file in report_phase then writing in final_phase.


Regression guard template

systemverilog
// Drop into base_test — catches silent false passes early
function void check_phase(uvm_phase phase);
  super.check_phase(phase);
  if (env.total_txns == 0)
    `uvm_error("CHECK", "REGRESSION GUARD: zero transactions")
  uvm_report_server svr = uvm_report_server::get_server();
  if (svr.get_severity_count(UVM_ERROR) > 0)
    `uvm_info("CHECK_DBG", "errors already pending before test check", UVM_MEDIUM)
endfunction