Part 2 · Phases & Lifecycle · Intermediate

Phase Callback Signatures: Exact Names and Types

The precise method names, return types, and uvm_phase argument for every common phase — and how silent failures happen when signatures drift.

The canonical signature table

UVM only overrides methods that exactly match the virtual declaration in

uvm_component. A one-character typo creates a new method that the scheduler never calls.

systemverilog

class my_comp extends uvm_component;
  `uvm_component_utils(my_comp)

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
  endfunction
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
  endfunction
  function void end_of_elaboration_phase(uvm_phase phase);
    super.end_of_elaboration_phase(phase);
  endfunction
  function void start_of_simulation_phase(uvm_phase phase);
    super.start_of_simulation_phase(phase);
  endfunction
  task run_phase(uvm_phase phase);
    super.run_phase(phase);
  endtask
  function void extract_phase(uvm_phase phase);
    super.extract_phase(phase);
  endfunction
  function void check_phase(uvm_phase phase);
    super.check_phase(phase);
  endfunction
  function void report_phase(uvm_phase phase);
    super.report_phase(phase);
  endfunction
  function void final_phase(uvm_phase phase);
    super.final_phase(phase);
  endfunction
endclass

diagram

[UVM][PHASE] signature checklist

return type:
  function void for function phases
  task (no void) for run_phase

name:
  <phase>_phase exactly — not build() or run()

argument:
  uvm_phase phase — required

virtual:
  implied by override — must match base

Key takeaways

Copy signatures from uvm_component verbatim until muscle memory forms.
Typos fail silently — your code runs but base empty implementation wins.
function vs task mismatch is either compile error or silent non-override.

Common pitfalls

build_phase() missing uvm_phase argument.
run_phase declared as function void.
end_of_elab_phase abbreviated name — scheduler ignores it.

Silent failure examples

Wrong name

systemverilog

// BUG: scheduler never calls this
function void build(uvm_phase phase);
  `uvm_info("BUILD", "custom build", UVM_LOW)
endfunction

// CORRECT:
function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  `uvm_info("BUILD", "real build", UVM_LOW)
endfunction

Wrong type

systemverilog

// BUG: does not override uvm_component::task run_phase
function void run_phase(uvm_phase phase);
  // compile error in strict environments, or wrong binding
endfunction

Detection workflow

Add distinctive uvm_info as first line of suspected phase.
Run with +UVM_PHASE_TRACE — if your message never appears, signature is wrong.
Compare against uvm_component source or IDE outline.
Fix name/type/argument, re-run trace before functional debug.

diagram

[PHASE] signature debug in 60 seconds

1) add `uvm_info("SIG_TEST", "build entered", UVM_NONE) in build_phase
2) sim +UVM_PHASE_TRACE
3) if SIG_TEST absent -> signature bug, not functional bug

Key takeaways

Silent override failure is a top-three UVM debug time sink.
SIG_TEST print plus phase trace diagnoses in one run.
When behavior 'ignores' your phase code, check signature before logic.

Common pitfalls

Debugging TLM null handles when build_phase override never ran.
Refactoring method names without scheduler-compatible names.
Assuming `uvm_component_utils macro auto-creates phase methods — it does not.

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