These open most CDC interviews. The interviewer is calibrating your mechanism thinking: short questions, and every strong answer names the flop-level behaviour before the pattern.
Field | Answer |
|---|---|
Interviewer is testing | whether you describe the physics or recite the word. |
Bad answer | "It is when a signal is unstable between clock domains." |
Better answer | "A flop sampling a changing input can resolve slowly or to an intermediate voltage, and downstream logic can read different values." |
Strong answer (a 4) | Adds the assumption (unrelated clocks, setup-hold violation), the trade-off (extra synchroniser stages buy settling time at latency cost, never certainty), and the evidence (resolution-time analysis, not simulation). |
Follow-ups | What lengthens settling; why simulation never shows it. |
Common trap | Calling metastability a CDC failure mode among others without saying it is the root physics. |
Evidence to cite | Structural check plus resolution-time argument. |
Taught in |
Field | Answer |
|---|---|
Interviewer is testing | The settling-time argument. |
Bad answer | "Two flops are safer than one." |
Better answer | "The first flop may resolve late; the second samples it a full destination period later, so it almost always sees a settled value." |
Strong answer (a 4) | Adds that the second flop buys time, not correctness, prices a third stage in latency against failure-rate margin, and cites the no-logic-between-flops rule. |
Follow-ups | When is three justified; what breaks if logic sits between the flops. |
Common trap | "Two flops remove metastability". |
Evidence to cite | Structural legality check plus the MTBF-resolution argument. |
Taught in |
Field | Answer |
|---|---|
Interviewer is testing | Honest numeracy. |
Bad answer | "More flops means infinite MTBF." |
Better answer | "MTBF grows exponentially with available settling time and degrades with faster clocks and higher data rates; it is a rate, not a guarantee." |
Strong answer (a 4) | Adds the trade-off (frequency, activity, and stage count pull in different directions), refuses to invent parameters, and labels any worked number illustrative. |
Follow-ups | What a third flop buys; why two designs with the same synchroniser have different MTBF. |
Common trap | Quoting a threshold as a signoff rule. |
Evidence to cite | The illustrative worked example, never a field measurement. |
Taught in |
Field | Answer |
|---|---|
Interviewer is testing | Definition discipline. |
Bad answer | "Signals between different frequencies." |
Better answer | "A signal launched by a flop on one clock net and captured by a flop on another." |
Strong answer (a 4) | Adds that identical frequencies on independent oscillators still cross, divided and gated clocks are different nets, and the domain is decided by the capture flop's net. |
Follow-ups | Divided clock to its source, yes or no; same net different branches. |
Common trap | "Same frequency, same domain". |
Evidence to cite | The crossing list from structural analysis, which is only as complete as the clock list. |
Taught in |
Field | Answer |
|---|---|
Interviewer is testing | Methodology maturity. |
Bad answer | "Yes, with enough coverage." |
Better answer | "No: ideal clocks have no setup-hold window, so simulation cannot show metastability, and sampled skews prove nothing about unsampled ones." |
Strong answer (a 4) | Adds what simulation can do (protocol behaviour, both directions, metastability-aware models) and names the missing evidence (structural analysis, formal proof). |
Follow-ups | What a metastability-aware model proves; what gate-level skew runs add. |
Common trap | Quoting randomised-skew run counts as confidence. |
Evidence to cite | Structural report plus formal results; simulation is supporting. |
Taught in |
Field | Answer |
|---|---|
Interviewer is testing | Classification before design. |
Bad answer | "Synchronise everything with two flops." |
Better answer | "A level held stable across samples needs settling only; a pulse narrower than the destination period can be missed entirely, so it needs toggle, stretch, handshake, or FIFO." |
Strong answer (a 4) | Adds the direction mirror (slow-to-fast risks duplication), prices each scheme, and cites the spacing rule as evidence. |
Follow-ups | Back-to-back pulses; a pulse into a faster clock. |
Common trap | Answering "pulse" without asking about width and spacing. |
Evidence to cite | Width-against-period analysis plus the synchroniser report. |
Taught in |
Field | Answer |
|---|---|
Interviewer is testing | Whether structure arguments are fluent. |
Bad answer | "It adds delay, so still fine." |
Better answer | "Defect: the second flop samples a function of a possibly still-resolving node, so the settling argument collapses." |
Strong answer (a 4) | What a 4 sounds like: "Assumption: the first flop resolved late near the destination edge. Mechanism: the logic output is still moving when the second flop samples, and worse, the logic fans the resolving node to several loads that settle differently, so the failure is divergence, not just delay. Trade-off: re-registering costs a cycle and fixes the class; waiving saves nothing because no evidence can bound it. Evidence: the structural check for logic between synchroniser flops, which exists precisely because this shape is never acceptable." |
Follow-ups | Reset synchronisers and the same rule; what a legal waiver looks like (there is none). |
Common trap | "Small logic is fine". |
Evidence to cite | The structural rule violation. |
Taught in |
Q1/Q2 (the physics and the circuit) with Q5 (what proves it): mechanism first, then the method that checks it. That ordering is the whole interview habit in miniature.