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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
    • CDC/RDC Whiteboard Framework
    • CDC/RDC Framework Drills
    • Scenario: Metastability Bug
    • Scenario: Metastability Escape in Silicon Bring-up
    • Scenario: Async FIFO Pointer Mismatch
    • Scenario: Waiver Debate
    • Scenario: RDC Waiver Under Tapeout Pressure
    • CDC/RDC Interview Q&A Bank
      • Fundamentals Q&A
      • Protocols and FIFO Q&A
      • Reconvergence and Multi-Bit Q&A
      • Reset and RDC Q&A
      • Signoff and Methodology Q&A
    • CDC/RDC Interview Q&A Bank (Expanded)
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹CDC/RDC Interview Q&A Bank
  1. Topics
  2. CDC & RDC
  3. CDC and RDC Interview Prep
  4. CDC/RDC Interview Q&A Bank
  5. Protocols and FIFO Q&A

Part 10 · Interview Prep · All levels

Protocols and FIFO Q&A

Seven questions on pulse synchronisers, handshakes and async FIFOs, with graded answers.

On this page

    Protocol questions test rate reasoning: every scheme has a spacing or throughput assumption, and the strong answer states it before the interviewer asks.

    Q1: A one-cycle pulse must cross from fast to slow. Options?

    Field

    Answer

    Interviewer is testing

    Scheme selection.

    Bad answer

    "Two-flop synchroniser on the pulse."

    Better answer

    "Direct capture loses it between slow edges; use a toggle synchroniser with a spacing rule, or a handshake."

    Strong answer (a 4)

    Assumes asynchronous clocks and unknown spacing, prices toggle (cheap, latent, spacing-bound) against handshake (any spacing, acknowledgement cost), and cites width analysis plus the structural report.

    Follow-ups

    Minimum spacing for toggle; what changes slow-to-fast.

    Common trap

    Stretching the pulse without a spacing argument.

    Evidence to cite

    Spacing proof plus synchroniser check.

    Taught in

    Why Pulses Need Help and Toggle Synchronizer

    Q2: Sketch the toggle synchroniser and state its contract.

    Field

    Answer

    Interviewer is testing

    Precise pattern knowledge.

    Bad answer

    "Toggle something and detect the edge."

    Better answer

    "Source toggles a bit per event; two-flop synchronise the toggle; destination edge-detects into a one-cycle strobe."

    Strong answer (a 4)

    Adds the contract (events spaced so each toggle level is visible, destination period assumptions, reset to a known toggle value) and the failure when the contract breaks (merged events).

    Follow-ups

    Reset values on both sides; back-to-back behaviour.

    Common trap

    Forgetting reset: mismatched initial toggle states fabricate a phantom event.

    Evidence to cite

    Assertion that every toggle yields exactly one strobe.

    Taught in

    Toggle Synchronizer

    Q3: Two-phase versus four-phase handshake: compare them.

    Field

    Answer

    Interviewer is testing

    Trade-off fluency.

    Bad answer

    "Four-phase is better."

    Better answer

    "Two-phase signals on transitions so every edge carries information; four-phase returns to idle each transfer, simpler to reason about at lower throughput."

    Strong answer (a 4)

    Prices them (transitions per transfer, idle-state observability, debug ease), states when each wins, and names the shared liveness obligation: every request gets exactly one acknowledge.

    Follow-ups

    Valid/ready across domains; what stalls each scheme.

    Common trap

    Claiming one is "safer" without a throughput or complexity price.

    Evidence to cite

    Formal liveness proof plus stall coverage.

    Taught in

    Four-Phase Req/Ack and Two-Phase Toggle

    Q4: When does crossing data need a FIFO rather than a handshake?

    Field

    Answer

    Interviewer is testing

    Throughput reasoning.

    Bad answer

    "FIFOs are for big data."

    Better answer

    "When transfers are frequent or bursty enough that per-transfer acknowledgement throttles the link: the FIFO decouples the rates and absorbs bursts."

    Strong answer (a 4)

    Adds the depth argument (cover the bursts the reader cannot drain while flags propagate), prices area and flag latency, and names reset alignment as part of the answer.

    Follow-ups

    Who generates full and empty, and where.

    Common trap

    "Deeper is always safer" without area or latency cost.

    Evidence to cite

    Depth analysis plus full/empty proof.

    Taught in

    Depth Sizing

    Q5: Why Gray pointers, and what breaks if the depth is not a power of two?

    Field

    Answer

    Interviewer is testing

    Boundary knowledge of the standard answer.

    Bad answer

    "Gray code is required for FIFOs."

    Better answer

    "Gray changes one bit per step so a sampled pointer is old or new, never torn; naive non-power-of-two ranges wrap through multi-bit jumps."

    Strong answer (a 4)

    Explains the wrap path (the standard binary-to-Gray construction assumes the full sequence), states the disciplined alternatives, and cites the transition assertion as evidence.

    Follow-ups

    Who checks the one-bit property; full/empty comparison placement.

    Common trap

    "Gray fixes any counter".

    Evidence to cite

    Pointer-transition assertion plus structural report.

    Taught in

    Gray Pointers in Signoff and Non-Power-of-Two Depths

    Q6: Where are full and empty generated, and why there?

    Field

    Answer

    Interviewer is testing

    Reconvergence discipline.

    Bad answer

    "Wherever convenient."

    Better answer

    "Empty in the read domain from the local read pointer and the synchronised write pointer; full mirrored in the write domain."

    Strong answer (a 4)

    Adds why: each flag compares a local value against one synchronised copy, so no gate ever combines two fresh crossings.

    Follow-ups

    The latency consequence (conservative flags); reset values that start empty.

    Common trap

    One shared comparator.

    Evidence to cite

    Structural reconvergence check on the pointer paths.

    Taught in

    Full and Empty

    Q7 (hardest): prove your FIFO never loses or duplicates data under any clock alignment.

    Field

    Answer

    Interviewer is testing

    Proof thinking.

    Bad answer

    "We tested it heavily."

    Better answer

    "Simulation under traffic plus metastability-aware models shows no loss or duplication."

    Strong answer (a 4)

    What a 4 sounds like: "Assumption: arbitrary phase and any resolution of each crossing. Mechanism of the proof: Gray pointers make every sample old-or-new, single-domain comparisons make flags conservative, so writes only enter non-full slots and reads only leave non-empty ones. Trade-off: the proof covers the protocol, not the flop physics; the physics is covered by the synchroniser legality check. Evidence: formal properties on full/empty against the synchronised pointers, the transition assertion, and traffic simulation as behavioural support, in that order."

    Follow-ups

    What the formal model abstracts away; ECO impact on the proof.

    Common trap

    Presenting simulation as the proof.

    Evidence to cite

    Formal plus structural, simulation supporting.

    Taught in

    Formal Protocol Checks and Metastability-Aware Simulation

    Common pitfall

    Memorising FIFO internals without the rate argument. Interviewers vary the rates to break memorised answers; the depth-from-rate-and-latency habit survives any numbers.

    Check yourself What single assumption underlies Q2, Q4, and Q5?

    The spacing and rate contract: toggles need spaced events, FIFOs need depth for the burst rate, Gray needs one step per sample. Every protocol answer is a contract plus its enforcement.

    Related topics

    • Next: Reconvergence and Multi-Bit Q&A

    • Full and empty

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    See also

    • Reset and RDC Q&A
    • Signoff and Methodology Q&A