VLSI DV Interview Puzzles · All levels

Overlap vs Non-Overlap

Statement: on req, gnt should be high in the same sampled cycle. Timeline: C30 req=1 gnt=1, C31 gnt=0. Evaluate both properties.

Puzzle

Difficulty: Easy · Puzzle 1 of 6 · Topic: Implication Puzzles

Statement: on req, gnt should be high in the same sampled cycle. Timeline: C30 req=1 gnt=1, C31 gnt=0. Evaluate both properties.

Code

systemverilog

property p_overlap;
  @(posedge clk) req |-> gnt;
endproperty

property p_nonoverlap;
  @(posedge clk) req |=> gnt;
endproperty

Hint

Compare consequent sampling cycle for |-> vs |=>.

Step-by-step solution

diagram

1) For p_overlap, gnt is checked at C30 and is 1, so overlap passes.
2) For p_nonoverlap, gnt is checked at C31 and is 0, so non-overlap fails.
3) Same waveform yields different outcomes purely from implication operator choice.

Answer

Answer: PASS for p_overlap, FAIL for p_nonoverlap - |-> checks same cycle, |=> checks next cycle.

Why candidates get it wrong

This is the most common interview slip: people remember arrows visually, but not their sampling offsets.

Interviewer follow-up

If gnt were high at both C30 and C31, what would each property report?

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