VLSI DV Interview Puzzles · All levels

Pure Vacuity

Property intent: every req must be granted within 0 to 2 cycles. In this test, req never becomes 1. Determine the verdict.

Puzzle

Difficulty: Easy · Puzzle 2 of 6 · Topic: Implication Puzzles

Property intent: every req must be granted within 0 to 2 cycles. In this test, req never becomes 1. Determine the verdict.

Code

systemverilog

property p_vacuous;
  @(posedge clk) req |-> ##[0:2] gnt;
endproperty

Hint

Ask whether the antecedent ever spawns a checking thread.

Step-by-step solution

diagram

1) req is never true at a sampled clock edge.
2) No implication attempts are triggered.
3) With no triggered antecedent, implication succeeds vacuously.

Answer

Answer: VACUOUS-PASS - antecedent never triggers, so no failing obligation is created.

Why candidates get it wrong

Vacuous pass is logically valid but dangerous if used as evidence of functional correctness without coverage.

Interviewer follow-up

What companion cover/assert would you add to ensure this property is meaningfully exercised?

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