AXI4-Lite removes burst and ID signals: each request describes one data transfer, and responses are returned in order. Implementations can still support more than one outstanding transfer within the protocol's ordering and buffering rules. The reduced signal/ordering contract can simplify endpoints, but throughput and complexity depend on the complete path.
Register and configuration blocks are common AXI4-Lite users. A low-rate data mover could also use it if its single-transfer throughput, latency and outstanding behaviour meet the product requirement; high-bandwidth DMA commonly benefits from full AXI bursts. Choose by measured traffic and implementation cost rather than a blanket block-type ban.
AWPROT and ARPROT carry protection attributes. AXI4-Lite has no AWCACHE or ARCACHE signals; its accesses have fixed Non-modifiable, Non-bufferable attributes, equivalent to AxCACHE=0b0000 on full AXI.
Write response (B) is required even for single-beat writes.
Some slaves require WSTRB=all-ones for writes — check IP docs.
AXI4-Stream moves data without per-transfer addresses. TVALID and TREADY define beat acceptance. When implemented, TLAST can mark a packet boundary, TKEEP qualifies byte lanes, and TID/TDEST/TUSER carry stream, routing or application-defined context. The source and destination must agree which optional signals and semantics form their interface contract.
Ideal for video pipelines, DSP chains, and NPU data feeders where data flows in order and addressing is implicit in the pipeline structure.
AXI-STREAM PACKET
TVALID ___|‾‾|_|‾|_|‾|_|‾‾‾‾|___
TDATA | B0 | B1 | B2 | B3 (TLAST) |
TKEEP | FF | FF | FF | FF |
TLAST on final beat = packet boundaryAWPROT and ARPROT carry protection attributes. AXI4-Lite has no AWCACHE or ARCACHE signals; its accesses have fixed Non-modifiable, Non-bufferable attributes, equivalent to AxCACHE=0b0000 on full AXI.
Write response (B) is required even for single-beat writes.
Some slaves require WSTRB=all-ones for writes — check IP docs.