A width converter must preserve the accepted byte sequence and the agreed packet/sideband semantics. A 128-to-64 conversion can emit two narrower transfers for one full input beat; partial final beats require correct TKEEP mapping when that signal is present. TLAST must remain associated with the final output transfer representing that packet boundary.
A stream switch needs a specified policy for every accepted TDEST value it supports: route, backpressure, explicit error/reporting path, or another documented action. Do not assume an unmatched destination is silently dropped, and do not accept data unless the implementation can honour its contract.
A finite stream FIFO absorbs bounded burst/rate mismatch but cannot prevent backpressure under an indefinitely larger arrival rate or service pause.
Pipeline and conversion stages must preserve, transform or intentionally discard TUSER according to the documented application contract.
DMA engines often bridge AXI (addressed) to AXI-Stream (datapath).