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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
    • APB & AHB Basics
    • AXI Channels & Transfers
    • AXI-Lite & AXI-Stream
      • AXI-Lite & AXI-Stream: Concepts
      • AXI-Lite & AXI-Stream: Integration
      • AXI-Lite & AXI-Stream: Debug
      • AXI-Lite & AXI-Stream: Interview
    • AMBA Integration Debug
    • AMBA Family (APB / AHB / AXI): Tricky Q&A
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←AXI-Lite & AXI-Stream
  1. Topics
  2. Bus Protocols
  3. AMBA Family (APB / AHB / AXI)
  4. AXI-Lite & AXI-Stream
  5. AXI-Lite & AXI-Stream: Debug
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    Interface ProtocolsAll levels

    AXI-Lite & AXI-Stream: Debug

    Debug for AXI-Lite & AXI-Stream.

    Primary debug scenario

    Symptom: Video pipeline stalls mid-frame. Upstream produces data. Downstream never sees TLAST.

    Triage steps

    1. Count beats since last TLAST — is upstream sending the right packet length?

    2. Check TREADY backpressure — is downstream stalling?

    3. If width converter in path: verify TLAST isn't swallowed during conversion.

    4. Check TDEST routing if stream switch is in the path.

    5. Reduce to single-packet test with known beat count.

    Common pitfalls

    • TLAST missing on final beat — downstream waits forever for packet end.

    • Choosing AXI4-Lite for a data mover without checking single-transfer throughput and outstanding limits.

    • Ignoring TKEEP on odd-sized final beats.

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    See also

    • AXI-Lite & AXI-Stream: Concepts