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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
    • ACE Coherent Transactions
      • ACE Coherent Transactions: Concepts
      • ACE Coherent Transactions: Integration
      • ACE Coherent Transactions: Debug
      • ACE Coherent Transactions: Interview
    • Snoop & Cache Maintenance
    • CHI Topology Basics
    • Coherence Fabric Debug
    • Coherence Fabrics (ACE / CHI): Tricky Q&A
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←ACE Coherent Transactions
  1. Topics
  2. Bus Protocols
  3. Coherence Fabrics (ACE / CHI)
  4. ACE Coherent Transactions
  5. ACE Coherent Transactions: Concepts
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    Interface ProtocolsAll levels

    ACE Coherent Transactions: Concepts

    Concepts for ACE Coherent Transactions.

    Core concepts

    ACE channel extensions

    ACE adds three snoop channels to AXI: AC (snoop address from interconnect to caches), CR (snoop response), and CD (snoop data). A coherent transaction can require snoop and/or memory actions according to its type, shareability domain and the interconnect's tracked state; this need not mean broadcasting every transaction to every cache.

    AxDOMAIN identifies the transaction's shareability domain, while other attributes and transaction type complete the contract. A Non-shareable transaction is outside shared-cache coherence for that access; it is not inherently faster. A Shareable attribute alone does not prove that every required agent, region mapping and software ownership rule is configured correctly.

    Diagram
    ACE SNOOP FLOW
    
    RN (master) --AR/Aw--> ICN (interconnect)
                              |
                         AC (snoop addr) --> peer caches
                         CR (snoop resp) <-- peer caches
                         CD (snoop data) <-- peer caches
                              |
                         AR/R or AW/W completes with coherent data

    Coherent read and write types

    ReadShared: fetch line, other caches may keep shared copy. ReadUnique: fetch line, invalidate other copies. WriteUnique: write with exclusive ownership. WriteBack: evict dirty line to memory.

    Each type triggers different snoop responses. A ReadUnique that gets a dirty copy from another cache receives data via CD channel instead of going to memory.

    • ACE barrier transactions/fields have defined domain and completion semantics; map them to the selected architecture/software ordering contract rather than calling them a universal fence.

    • DVM (Distributed Virtual Memory) ops for TLB/cache maintenance across cores.

    • Incorrect shareability can change coherence participation or traffic; demonstrate the resulting outcome with the complete region and software contract.

    Key takeaways

    • ACE barrier transactions/fields have defined domain and completion semantics; map them to the selected architecture/software ordering contract rather than calling them a universal fence.

    • DVM (Distributed Virtual Memory) ops for TLB/cache maintenance across cores.

    • Incorrect shareability can change coherence participation or traffic; demonstrate the resulting outcome with the complete region and software contract.

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    See also

    • ACE Coherent Transactions: Debug
    • ACE Coherent Transactions: Interview