Define which CPU clusters, accelerators and device paths participate in hardware coherence for each region. A non-coherent path needs an explicit software ownership and cache-maintenance contract; it is not inherently faster. Coherence concerns values at each location, while the memory consistency model constrains ordering across locations.
DMA buffers that cross coherent and non-coherent views need an explicit platform ownership/mapping contract. Use the platform DMA interfaces for allocation, mapping and synchronisation so any required maintenance and barriers match direction and lifecycle.
Map every memory region to a shareability domain in the address map.
Distinguish device registers from DMA data buffers; use the platform's specified memory type and shareability for each.
Use the platform DMA and synchronisation interfaces; hardware coherence does not replace software ordering or ownership rules.