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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
    • ACE Coherent Transactions
    • Snoop & Cache Maintenance
      • Snoop & Cache Maintenance: Concepts
      • Snoop & Cache Maintenance: Integration
      • Snoop & Cache Maintenance: Debug
      • Snoop & Cache Maintenance: Interview
    • CHI Topology Basics
    • Coherence Fabric Debug
    • Coherence Fabrics (ACE / CHI): Tricky Q&A
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Snoop & Cache Maintenance
  1. Topics
  2. Bus Protocols
  3. Coherence Fabrics (ACE / CHI)
  4. Snoop & Cache Maintenance
  5. Snoop & Cache Maintenance: Concepts
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    Interface ProtocolsAll levels

    Snoop & Cache Maintenance: Concepts

    Concepts for Snoop & Cache Maintenance.

    Core concepts

    MESI state machine

    Modified: line is dirty, only this cache has it. Exclusive: line is clean, only this cache has it. Shared: line is clean, multiple caches may have it. Invalid: line is not in this cache.

    Transitions happen via snoops and local accesses. A write to a Shared line requires upgrade to Modified (invalidate other copies). A snoop invalidate moves a line to Invalid.

    Diagram
    MESI STATES
    
    Invalid <--snoop inv-- Shared <--snoop/shared read-- Exclusive
       |                      |                              |
       +--local read miss----+                              |
       |                      +--local write--> Modified <--+
       +--local write miss---------------------------------+

    Cache maintenance operations

    Conceptually, a clean makes dirty data visible at a specified point while retaining a valid copy; an invalidate removes a local copy under an ownership contract; a combined operation performs both in a defined order. Exact instruction names, cache levels, target point (such as PoC/PoU), completion and effects are architecture-specific—'flush' is too ambiguous without those details.

    For non-coherent DMA, follow the platform DMA API for mapping, synchronisation and ownership transfer. CPU-produced data may need cleaning before device reads; device-produced data may require invalidation before CPU reads. The exact sequence also depends on direction, barriers and shared-line ownership. Do not apply a universal flush recipe to hardware-coherent DMA or invalidate unrelated dirty CPU data.

    • Use the architecture-reported maintenance granule and alignment rules; do not assume a universal 64-byte line.

    • PoC (Point of Coherency) vs PoU (Point of Unification) matters for maintenance scope.

    • Hardware coherency doesn't eliminate all software maintenance needs.

    Key takeaways

    • Use the architecture-reported maintenance granule and alignment rules; do not assume a universal 64-byte line.

    • PoC (Point of Coherency) vs PoU (Point of Unification) matters for maintenance scope.

    • Hardware coherency doesn't eliminate all software maintenance needs.

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    See also

    • Snoop & Cache Maintenance: Debug
    • Snoop & Cache Maintenance: Interview