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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
    • ACE Coherent Transactions
    • Snoop & Cache Maintenance
      • Snoop & Cache Maintenance: Concepts
      • Snoop & Cache Maintenance: Integration
      • Snoop & Cache Maintenance: Debug
      • Snoop & Cache Maintenance: Interview
    • CHI Topology Basics
    • Coherence Fabric Debug
    • Coherence Fabrics (ACE / CHI): Tricky Q&A
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Snoop & Cache Maintenance
  1. Topics
  2. Bus Protocols
  3. Coherence Fabrics (ACE / CHI)
  4. Snoop & Cache Maintenance
  5. Snoop & Cache Maintenance: Integration

Interface ProtocolsAll levels

Snoop & Cache Maintenance: Integration

Integration for Snoop & Cache Maintenance.

Integration in practice

Software coherency contract

Hardware coherence does not replace publication ordering, ownership, access control or architecture rules for changing memory attributes. For DMA mapping, remapping and boot-stage handoff, follow the platform interfaces and transition sequence; some coherent paths need no explicit data-cache maintenance for ordinary transfers, while other transitions do.

  • Document which memory regions are hardware-coherent vs software-managed.

  • DMA allocation/mapping must satisfy the platform's granule, alignment, attribute and ownership requirements.

  • Bootloader-to-kernel handoff must define visibility, attributes and required maintenance/synchronisation for each region.

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See also

  • Snoop & Cache Maintenance: Interview